Reliability research

The test center studies the physics of failure mechanisms occurring in contemporary EEE structures including CMOS-technology based integral circuits with minimum feature sizes to 0.09 µm in order to update and improve the accelerated reliability testing techniques.
Degradation of electrical parameters is studied during EEE testing in order to investigate EEE reliability estimability under restrictions of limited time and small sample sizes. Prediction Degradation failure prediction methods are developed using time-series models and digital adaptive filters.
The test center studies the possibility to implement the following methods to estimate the EEE reliability according to the results of small sample size tests:
  • information method;
  • parametric function method;
  • test results summation method;
  • statistical hypothesis testing method,
  • experimental design theory based method;
  • contribution method;
  • Bernoulli distribution based method;
  • Bayes theorem (formula) based methood.

For the last 10 years, the statistics for foreign EEE accelerated reliability testing results have been accumulated and summarized. The obtained statistics allow to predict experimentally-confirmed reliability of the EEE being certified and compare it with predictions of the leading foreign EEE manufacturing companies. For the last 5 years, more than 20 standards of various levels have been developed and put in force: from company standards to GOST



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